In modern computer systems, power density and scalability issues represent some of the most significant obstacles to increased system performance. For reliability, the supply voltage Vdd must come down and the threshold voltage must come up. Consequently, performance is being rapidly squeezed between the two. In addition, with the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power and ultra-low power transistor devices and systems. To meet this demand devices are emerging which have extremely low threshold voltages.
There are a number of factors that contribute to the magnitude of a device's threshold voltage. For example, to set a device's threshold voltage near zero, light doping and/or counter doping in the channel region of the device may be provided. However, due to processing variations, the exact dopant concentration in the channel region can vary slightly from device to device. Although these variations may be slight, they can shift a device's threshold voltage by a few tens or even hundreds of millivolts. Further, dimensional variations, such as oxide thickness, channel width, channel length, charge trapping in materials and interfaces, and environmental factors, such as operating temperature fluctuations, can shift the threshold voltage.
Lowering the threshold voltage of a device typically decreases active power dissipation by permitting the same performance to be achieved at a lower supply voltage. However, lowering the threshold voltage of a device normally increases standby power dissipation by increasing device leakage and devices having low threshold voltages can leak so much current when their circuits are in a sleep or standby mode that the gains made by lowering the threshold voltage are outweighed by the power lost to leakage.
Consequently, it is particularly desirable in low-threshold devices to provide a mechanism for tuning the threshold voltage to account for these and other variations. Tuning the threshold voltage of a device can be accomplished using back biasing, i.e. controlling the potential between a device's well and source. See James B. Burr, “Stanford Ultra-Low Power CMOS,” Symposium Record, Hot Chips V, pp. 7.4.1–7.4.12, Stanford, Calif. 1993, which is incorporated, in its entirety, herein by reference. Back-biasing is used to electrically tune the transistor thresholds by reverse biasing the bulk of each MOS transistor, relative to the source, to adjust the threshold potentials. Typically, the potential will be controlled through isolated contacts to the source and well regions together with circuitry necessary for independently controlling the potential of these two regions.
FIG. 1A illustrates a prior art device 100A in which each of an NFET 101 and a PFET 102 essentially constitutes a four-terminal device. NFET 101 is made up of an N-region source 103, a gate electrode 104, an N-region drain 105, and a P-bulk material 106. Similarly, PFET 102 includes P-region source 108, a gate electrode 109 and a P-region drain 110 formed in an N well 111. the device of FIG. 1A also includes a P plug that forms a well tie 112 for P-bulk material 106, and an N plug that forms a well tie 113 for N-well 111.
In the back-biased CMOS design of FIG. 1A, well tie 112 of bulk material 106 is electrically isolated from source 103 of NFET 101 by providing a separate metallic rail contact 116 which is spaced from metallic rail contact 114 of source 103. Rail contact 116 is coupled to a bias voltage source Vpw. Likewise, well contact 113 of N-well 111 is split off from source 108 of PFET 102 by providing a separate metallic rail contact 118 that is electrically isolated from metallic rail contact 115 of source 108. Rail contact 118 is coupled to a bias voltage source Vnw.
According to the structure of prior art device 100A, the substrate bias potential of NFET 101 is set by Vpw, and that of PFET 102 is set by Vnw. In other designs, a number of transistors are formed in a common well. In these designs, the bias potential may be routed within a surface well.
FIG. 1B illustrates a device 100B similar to device 100A of FIG. 1A, except that bulk material 106 of the NFET 101 in FIG. 1B is biased to Vpw by way of a metallic back plane 119, rather than by way of well tie 116 as shown in FIG. 1A.
FIG. 1C shows a portion of prior art back biased device 100A including NFET 101. In the discussion below, NFET 101 was chosen for illustrative purposes only. Those of skill in the art will recognize that PFET 102 could also have been chosen and that the discussion and effects discussed below would be equally applicable, with the exception that the polarities would be reversed.
In FIG. 1C, the well-known effect of coupling capacitance between gate 104 and bulk material 106 is represented by gate-bulk coupling capacitance 150 and the well known effects of coupling capacitance between drain 105 and bulk material 106 is represented by drain-bulk coupling capacitance 152. Due to gate-bulk coupling capacitance 150, there is a tendency for the voltage of bulk material 106, V-bulk, to track the voltage on gate 104. As discussed in more detail below, if this tracking were allowed, there is a tendency to raise V-bulk and decrease the threshold voltage of NFET 101 as device 101 turns on, and, as discussed above, lowering the threshold voltage of a device such as NFET 101 has several benefits. However, in the prior art, a significant amount of effort, and virtually all teaching, was directed to keeping V-bulk constant during a switching event and preventing significant changes in the potential of bulk material 106 during a switching event. To this end, it was taught that bulk material 106 should be the lowest resistance possible and that bulk material 106 should be coupled as directly as possible to ground or some other drain-off potential.
The main reason that the prior art taught keeping V-bulk constant, and bulk material 106 as low a resistive value as possible, is that in prior art CMOS designs two problems were always being dealt with: large impact ionization currents and/or latch up.
Impact ionization currents are created because the potentials in standard CMOS devices are high, on the order of 1.5 to 5.0 volts. At these potentials, charge carriers acquire so much kinetic energy that the impact of the carriers at the drain end of the channel can result in the generation of electron-hole pairs. Typically, in an NFET, the electrons move across the channel to the drain while the holes move into bulk material 106 thus creating potentially large sub-currents in bulk material 106. In the prior art, if bulk material 106 were composed of even moderately resistive material, these sub-currents would result in large voltage drops throughout bulk material 106.
FIG. 1D shows a graph of the natural log of the substrate current in an N-well (Inw) and P-well (Ipw) due to impact ionization as a function of the source to drain potential (Vds) of a device. It is worth noting for later reference that at a Vds of 1.0 volts (120) or less, there is virtually no impact ionization current, while at the typical prior art CMOS Vds of 1.5 (123) to 5.0 (125) volts the impact ionization current is relatively high.
In addition to minimizing the effects of impact ionization current, the prior art taught that bulk material 106 must be low resistance, and kept at a constant potential, to avoid latch-up. Latch-up is a well-known result of CMOS design that inherently includes parasitic bipolar transistors cross-coupled in the device. As a result of these parasitic bipolar transistors, if the potential of bulk material (Vpw) 106 becomes sufficiently large and forward biased, or if the n-well potential (Vnw) of n-well 111 (see FIG. 1A) becomes sufficiently lower than the supply voltage (Vdd), a short is created between ground (gnd) and supply voltage (Vdd). This short could draw enough current to not only shut down or “latch-up” the device, but in many cases, the current draw was large enough to physically destroy the device. Latch-up typically occurs in devices with supply voltages of 0.8 volts or greater. Note that in some cases, latch-up could be prevented even if the supply voltage is greater than 0.8V using back bias. A back biased bulk is much less likely to rise sufficiently above ground to turn on the parasitic NPN; likewise, a back biased N-well is much less likely to decrease sufficiently below Vdd to turn on the PNP.
Both impact ionization current and latch-up are well known to those of skill in the art. As a result of these known effects, prior art CMOS devices, and the entire teaching in the prior art, was directed to devices which minimize these effects by having low resistance bulk materials 106 and keeping the bulk potential, V-bulk, as constant as possible.
FIG. 1E shows the relationship between: the gate potential 160 (Vg 160) of gate 104 (FIG. 1C); the drain potential 170 (Vd 170) of drain 105; and the bulk potential 180 (V-bulk 180) in a device designed according to the prior art CMOS structures and teachings.
In FIG. 1E, at time T0: Vg 160 is at potential 161, typically near a digital zero; Vd 170 is at potential 171, typically near a digital one; and V-bulk 180 is at equilibrium potential 181, in one embodiment ground. In time interval 191, i.e., between T1 and T2, the device turns on and: Vg 160 rises along ramp 163 from potential 161, typically near digital zero, to potential 165, typically near digital one; at the same time, due to gate-bulk coupling capacitance 150, V-bulk 180 increases slightly from equilibrium potential 181, typically ground, to potential 183, typically greater than ground, but significantly less than digital one. In one embodiment, potential 183 is 10 to 100 millivolts greater than equilibrium potential 181.
During this same time frame, i.e., time interval 191, Vd 170 remains relatively constant at near digital one. From time T2 on, Vg 160 also remains relatively constant at near digital one. However, since the device being discussed is designed according to prior teachings to have a low resistance bulk material 106, at time T2, V-bulk 180 rapidly drops back to potential 181, the equilibrium potential. In one embodiment, V-bulk 180 drops back to equilibrium potential 181 in 10 to 100 pico-seconds, a small fraction of time interval 191.
In time interval 193, i.e., between time T3 and T4, the device is on and the drain potential is decreasing. Consequently, Vd 170 starts to fall from potential 171, typically near digital one, to potential 175, typically near digital zero, along ramp 173. Also in time interval 193, due to drain-bulk coupling capacitance 152, V-bulk 180 drops from equilibrium potential 181, typically ground, to a lower potential 187 along ramp 185 which tracks ramp 173. In one embodiment, potential 187 is 10 to 100 millivolts less than equilibrium potential 181.
During this same time frame, i.e., time interval 193, Vg 160 typically remains relatively constant at near digital one. From time T4 on, Vd 170 also remains relatively constant at near digital zero. However, since the device being discussed is designed according to prior art teachings to have a low resistance bulk material 106, at time T4, V-bulk 180 rapidly rises back to equilibrium potential 181. In one embodiment, V-bulk rises back to equilibrium potential 181 in 10 to 100 pico-seconds, a small fraction of time interval 193.
Note, in FIG. 1E, time interval 191 is shown graphically spaced from time interval 193, however those of skill in the art will recognize that in many cases time interval 191 will overlap with time interval 193 creating a more complex wave form. Consequently, the representation in FIG. 1E has been simplified for illustrative purposes.
A similar, but reversed, process takes place when the device turns off, i.e., when Vg 160 goes back to a digital zero and Vd 170 goes back to a digital one. Consequently, in prior art CMOS devices, and according to prior art teachings, V-bulk 180 remains relatively constant in response to a single switching event. As a result, the threshold voltages of prior art devices such as NFET 101, PFET 102 and prior art back biased devices 100A and 100B remain relatively constant in response to a given switching event. Therefore, while being very stable, prior art CMOS devices do not benefit from lower threshold voltages as the device turns on or relatively higher threshold voltages as the device turns off.
In contrast to prior art CMOS devices, such as NFET 101 and PFET 102 discussed above, with their relatively constant bulk material potential during a switching event and correspondingly constant threshold voltages, Partially Depleted Silicon On Insulator (PDSOI) devices have floating bulk potentials. Silicon-On-Insulator (SOI) devices are characterized by structures in which the silicon device layers are formed over an insulating film. FIG. 2A illustrates an exemplary configuration of such a device 200A. Device 200A of FIG. 2A includes an NFET 201 and a PFET 202 formed within a layer 236. Layer 236 is located along an oxide layer 208 which itself is formed atop a P+ bulk material 220. NFET 201 includes source and drain N-regions 203 and 205, respectively, a P-type channel 216 and a gate electrode 204. PFET 202 includes source and drain P-regions 208 and 210, respectively, an N-type channel 224 and a gate electrode 209. SOI devices, such as SOI device 200A, are characterized by low parasitic capacitances, as well as high dielectric isolation of the on-chip components.
A “partially depleted” SOI device refers to a structure in which the depletion region of the transistor does not extend all the way down to oxide layer 208. An example of this type of structure is shown in FIG. 2B. FIG. 2B shows a portion of a prior art partially depleted SOI NFET device 201B. In the discussion below, NFET 201B was chosen for illustrative purposes only. Those of skill in the art will recognize that a PFET device could also have been chosen and that the discussion and effects discussed below would be equally applicable, with the exception that the polarities would be reversed.
In FIG. 2B, the silicon layer 236B is relatively thick and the N-regions 203B and 205B are appropriately configured, typically through use of source-drain extensions, such that depletion region 228 is spaced from the upper surface of oxide layer 208B by a distance 230, i.e., only a portion of the P-region 216B is depleted. Consequently, when the gate potential is turned on, the potential of P-region 216B, below the depletion region 228, i.e., the “bulk region 206B” is pulled up, whereby the bulk material potential, V-bulk, of bulk material region 206B tracks the gate potential. This results in a forward biasing of the bulk region 206B that in turn decreases the threshold voltage of device 201B.
In FIG. 2C, the well-known effect of coupling capacitance between gate 204B and bulk material region 206B is represented by gate-bulk coupling capacitance 250 and the well known effects of coupling capacitance between drain 205B and bulk material region 206B is represented by drain-bulk coupling capacitance 252. Due to gate-bulk coupling capacitance 250, there is a tendency for the voltage of bulk material region 206B, V-bulk, to track the voltage on gate 204B.
FIG. 2D illustrates the well known floating body effect by showing the relationship between: the gate potential 260 (Vg 260) of gate 204B (FIG. 2B); the drain potential 270 (Vd 270) of drain 205B; and the bulk potential 280 (V-bulk 280) in a device such as partially depleted SOI device 201B designed according to the prior art structures and teachings.
In FIG. 2D, at time T0: Vg 260 is at potential 261, typically near a digital zero; Vd 270 is at potential 271, typically near a digital one; and V-bulk 280 is at potential 281. In time interval 291, i.e., between T1 and T2: Vg 260 rises along ramp 263 from potential 261, typically near digital zero, to potential 265, typically near digital one. At the same time, due to gate-bulk coupling capacitance 250, V-bulk 280 tracks Vg 260 and increases from equilibrium potential 281 to potential 283, typically greater than 281, and, in one embodiment, as high as a digital one greater than 281.
During this same time frame, i.e., time interval 291, Vd 270 remains relatively constant at near digital one. From time T2 to time T3, Vg 260 and V-bulk 280 remain relatively constant at their respective values 265 and 283.
In time interval 293, i.e., between time T3 and T4, Vd 270 starts to fall from potential 271, typically near digital one, to potential 275, typically near digital zero, along ramp 273. Also in time interval 293, due to drain-bulk coupling capacitance 252, V-bulk 280 partially tracks Vd 270 and drops from potential 283 to a lower potential 287, which, in one embodiment, is as much as a digital one below 283, along ramp 285, which tracks ramp 273. During this same time frame, i.e., time interval 293, Vg 260 typically remains relatively constant at near digital one. From time T4 on, Vd 270 remains at near digital zero.
Note, in FIG. 2D, time interval 291 is shown graphically spaced from time interval 293, however those of skill in the art will recognize that in many cases time interval 291 will overlap with time interval 293 creating a more complex wave form. Consequently, the representation in FIG. 2D has been simplified for illustrative purposes.
Importantly, from time T4 on, V-bulk 280 remains relatively constant at potential 287, which, in FIG. 2D, is a higher potential than the equilibrium potential 281. Note, however, that in other instances, it is possible that potential 287 will be lower than potential 281, depending on the relative magnitude of coupling capacitances 250 and 252. Consequently, V-bulk 280 typically does not return to its equilibrium potential 281 before the next clock and becomes unpredictable with each successive clock period. This is the essence of the floating body effect discussed above.
A similar, but reversed, process takes place as the device turns off, i.e., when Vg 260 goes back to a digital zero and Vd 270 goes back to a digital one. However, each period results in continued variation in the starting potential of V-bulk 280. Consequently, in prior art SOI devices, the benefits of V-bulk 280 tracking the gate potential Vg 260, i.e., lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off, are outweighed by the uncertainty of V-bulk 280, i.e., the floating body effect.
As discussed above, lowering the threshold voltage during switching of a device, such as NFET 201B, has several benefits including higher performance and/or lowering overall power consumption. However, in SOI devices, such as devices 200A and 201B, and, in particular, partially depleted SOI devices such as device 201B, when the bulk material potential, V-bulk 280, of bulk material region 206B tracks the gate, the bulk material potential, V-bulk 280, of bulk region 206B becomes an uncontrollable and unpredictable variable. Consequently, in contrast to standard CMOS devices discussed above, in PDSOI devices, the potential V-bulk cannot be known with any certainty, i.e., it floats. Therefore, the threshold voltage of the device can vary from clock to clock and period to period.
As discussed above, in prior art CMOS devices, it is taught that the bulk material, including any wells in the bulk material, should be as low resistance as possible and V-bulk should remain as relatively constant as possible to deal with large impact ionization currents and latch-up. Consequently, prior art CMOS structures could not benefit from a variable V-bulk which tracks the gate potential and thereby lowers the threshold voltage as the device turns on.
As also discussed above, while prior art partially depleted SOI devices did allow the potential of the bulk material, V-bulk, to track the gate potential and thereby lower the threshold voltage as the device turned on, the floating body effect meant that the device typically did not return to an equilibrium potential between clock periods. Therefore, neither V-bulk, nor the threshold voltage of the device, could be controlled or predicted.
What is needed is a device whose threshold voltage lowers as the device turns on and then rises as the device turns off, like a partially depleted SOI device, yet has the equilibrium stability of prior art CMOS devices so that V-bulk returns to a relatively known value within one clock period. Consequently, what is needed is a device that allows the bulk material potential to track the gate potential to lower the threshold voltage as the device turns on and raise the threshold voltage as the device turns off, yet allows the bulk material potential to be controlled and stabilize at an equilibrium potential between clock periods.